Lance...
     Thanks for digging into this. Here's some more info. The sizes in the
CMU lib are in microns. I looked at the layout for a few
cells and they did seem to agree with the area values in the .lib file.
(e.g. the inv_2x has area 60 in the .lib file and is 60 um**2 in layout)
So.... what units are the 5X numbers ?
   As for the wire models.. I added them from the ones used in 5x.. so your
concern about the size assumputions is valid. I suspect we need to apply a
scaling factor to them.  Let's talk about it tomorrow...
  As for capacity.. there is no hardset die size for the project.. Unlike
our rigid image concept, the MOSIS fab guys only give you minimum and
maximum die size limits.  I know that people have successfully done 500K
gate designs in this library. .. I'm more concerned about tool capacity..
routing especially. I don't think we'll get anywhere close to pushing the
absolute capacity.. but we could start looking at some hefty runtimes.
   Thanks again for your sluethwork...


-jc


"Lance D. Pickup" <[log in to unmask]> on 03/08/2000 12:55:51 PM

To:   [log in to unmask]
cc:   John M Cohn/Burlington/IBM@IBMUS, Jack Smith/Burlington/IBM@IBMUS,
      Mark D Lange/Burlington/IBM@IBMUS
Subject:  stdcell library sizes



I have examined the Synopsys library information for the CMU library
to determine if the area reports we are getting out make any sense.
I have come to the determination that the size values we are getting out
are scaled at least 10x and possibly 20-60x!  To get a concrete answer
to this question, we would need an answer to the question of for an
XX by XX mm chip, what is the capacity (in whatever units the library
designers chose) of the chip?

Anyway, here is a comparison between the CMU library and the IBM CMOS5S0
library.  All library elements were chosen to be single drive strength.
Not that these would actually correspond, but in general synthesis is
going to start with this drive strength and power up where it needs to,
so I think it's a fair comparison:

Element         CMU       IBM      Scale?
Inverter         60         1         60x
2w NAND          80         2         40x
4w NAND         120         4         30x
Scannable DFF   640         9*       ~70x
2:1 MUX         160         4         40x
4:1 MUX         380         8        ^50x

* IBM Scannable DFF requires an external clock splitter for every 10
or so latches, so the equivalent size may be slightly larger than 9.

Now obviously there are going to be differences in library design,
and the only question that really matters is what units are the
CMU library areas in and what is the capacity of the chip, but for
a ballpark apples to apples comparison, I would divide the sizes you
get out of Synopsys by 30-40 to get an IBM-like measure of size,
and know that we can fit approx. 1 million IBM gates onto a CMOS5S0
chip (albeit a LARGE chip!)

So, my 250K "cell" floating point unit is more like 7K IBM gates.
I think the murmurs heard from the peanut gallery can now be quelled
somewhat.

John, I notice the v32 library has wireload models in it.  Where did
these wireload models come from?  If they were copied from an IBM library
to be tweaked later, I would caution you that the area numbers need to
be similarly scaled or else they make no sense.  If these numbers come
from CMU, then I am scared again because it implies that the maximum
chip capacity is 2 million CMU cells (equiv to ~60K IBM cells which
is pretty small for a 0.35 micron technology!)

  ...Lance

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