John,

  The area units in the 5S library are in units of "standard cells".  I'm
not a circuit designer so I don't know what the ratio between standard
cells and square microns is, but it is defined somewhere (someone can
probably tell us).

  For those that don't know, a standard cell is a rectangular area of
silicon that contains several "background shapes" that are identical from
cell to cell.  Furthermore, you can place any standard cell next to another
standard cell and it will be "guaranteed" to meet ground rule constraints.
The background shapes I am talking about consist of things like an N-well,
a GND and VDD power bus that you can tap into, etc.  The chip is divided up
into millions (at least these days) of these standard cells.  A typical
standard cell in an IBM library is "tall and skinny".  Height-wise
it contains enough room for an NFET and a PFET plus area in between the
transistors and on top and below of the transistors for contacts, etc.
Width-wise there is typically only room for one or two transistors.
Typically the height of the standard cell is measured in terms of wiring
tracks which is to say how many metal wires can be run horizontally
across the cell.

  The ASIC library is made up of elements (inverter, nand, dff, etc) that
are designed to fit into an integral number of standard cells.  An inverter
usually takes just one cell since you only need 2 transistors.  For
larger circuits, you need to use more cells.  If your circuit needs even
just slightly more than an integral number of cells, too bad--you need to
extend it by an entire cell.  This is why they make the cells so skinny!

  The cells are designed such that if you put any two elements next to
each other, they will not interfere with each other from a ground-rule
standpoint.  Most elements are one cell high, but N cells wide.  The
placement program places the elements in rows.  I believe that every
other row is flipped so that the PFETs can share a common N-well.  And
there may be a space between the other rows for additional global wiring
tracks.

  I'm sure we will soon learn all the gory details of this.  I hope you
can see how there cannot be an exact "ratio" between the CMU and the IBM
libraries since many things would enter into it:  how small the circuits
were designed, the size of the CMU vs. IBM standard cell, etc.  One
library may have a fantastic DFF while the other may have a great INVERTER.
The real thing to consider here is what is the capacity of the chip AND as
John said, the tools themselves.

  ...Lance

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